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CD40105BMS

Part Number	CD40105BMS
Manufacturer	Intersil Corporation
Description	CMOS FIFO Register
Published	Mar 23, 2005
Detailed Description	CD40105BMS December 1992 CMOS FIFO Register Description CD40105BMS is a low-power ﬁrst-in-ﬁrst-out (FIFO) “elastic” sto...
Datasheet	CD40105BMS PDF File

Overview

CD40105BMS December 1992 CMOS FIFO Register Description CD40105BMS is a low-power ﬁrst-in-ﬁrst-out (FIFO) “elastic” storage register that can store 16 4-bit words.
It is capable of handling input and output data at different shifting rates.
This feature makes it particularly useful as a buffer between asynchronous systems.
Each word position in the register is clocked by a control ﬂipﬂop, which stores a marker bit.
A “1” signiﬁes that the position’s data is ﬁlled and a “0” denotes a vacancy in that position.
The control ﬂip-ﬂop detects the state of the preceding ﬂip-ﬂop and communicates its own status to the succeeding ﬂip-ﬂop.
When a control ﬂip-ﬂop is in the “0” state and sees a “1” in the preceding ﬂip-ﬂop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding ﬂip-ﬂop to “0”.
The ﬁrst and last control ﬂip-ﬂops have buffered outputs.
Since all empty locations “bubble” automatically to the input end, and all valid data ripple through to the output end, the status of the ﬁrst control ﬂip-ﬂop (DATA-IN READY) indicates if the FIFO is full, and the status of the last ﬂip-ﬂop (DATAOUT READY) indicates if the FIFO contains data.
As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.
Loading Data - Data can be entered whenever the DATA-IN READY (DIR) ﬂag is high, by a low to high transition on the SHIFT-IN (SI) input.
This input must go low momentarily before the next word is accepted by the FIFO.
The DIR ﬂag will go low momentarily, until that data have been transferred to the second location.
The ﬂag will remain low when all 16word locations are ﬁlled with valid data, and further pulses on the SI input will be ignored until DIR goes high.
Continued on next page Features • 4 Bits x 16 Words • High Voltage Type (20V Rating) • Independent Asynchronous Inputs and Outputs • 3-Stat...

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