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CD40193BMS

Part Number	CD40193BMS
Manufacturer	Intersil Corporation
Description	CMOS Presettable Up/Down Counters
Published	Mar 23, 2005
Detailed Description	CD40192BMS CD40193BMS December 1992 CMOS Presettable Up/Down Counters (Dual Clock With Reset) Description CD40192BMS Pr...
Datasheet	CD40193BMS PDF File

Overview

CD40192BMS CD40193BMS December 1992 CMOS Presettable Up/Down Counters (Dual Clock With Reset) Description CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated “D” type ﬂip-ﬂops connected as a counter.
The inputs consist of 4 individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RESET.
Four buffered Q signal outputs as well as CARRY and BORROW outputs for multiple-stage counting schemes are provided.
The counter is cleared so that all outputs are in a low state by a high on the RESET line.
A RESET is accomplished asynchronously with the clock.
Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET ENABLE control is low.
The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high.
The counter counts down one count on...

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