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CD40208BMS

Part Number	CD40208BMS
Manufacturer	Intersil Corporation
Description	CMOS 4 x 4 Multiport Register
Published	Mar 23, 2005
Detailed Description	CD40208BMS December 1992 CMOS 4 x 4 Multiport Register Description The CD40208BMS is a 4 x 4 multiport register contain...
Datasheet	CD40208BMS PDF File

Overview

CD40208BMS December 1992 CMOS 4 x 4 Multiport Register Description The CD40208BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses.
When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high impedance state.
The high impedance third state provides the outputs with the capability of being connected to the bus lines in a bus organized system without the need for interface or pull-up components.
When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines.
When WRITE ENABLE is low, the CLOCK is inhibited and no new data is entered.
In either case, the contents of any word may be accessed via the read address lines independent of the state of the CLOCK input.
The CD40208BMS types are supplied in hermetic 24-lead dual-in-line ceramic packages (D and F sufﬁxes), 24-lead dual-in-line plastic packages (E sufﬁx), 24-lead ceramic ﬂat packages (K sufﬁx), and in chip form (H sufﬁx).
The CD40208BMS is supplied in these 24-lead outline packages: Braze Seal DIP Ceramic Flatpack HNZ H4P Features • • • • • • High Voltage Types (20V Rating) One Input and Two Output Buses Unlimited Expansion in Bit and Word Directions Data Lines have Latched Inputs 3-State Outputs Separate Control of Each Bus, Allowing Simultaneous Independent Reading of any of Four Registers on Bus A and Bus B and Independent Writing Into any of the Four Registers 100% Tested for Quiescent Current at 20V Standardized, Symmetrical Output Characteristics 5V, 10V and 15V Parametric Ratings Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.
5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standards No.
13B, “St...

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