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KSZ8895MLX

Microchip
Part Number KSZ8895MLX
Manufacturer Microchip
Description Integrated 5-Port 10/100 Managed Ethernet Switch
Published Feb 8, 2017
Detailed Description KSZ8895MQX/RQX/FQX/MLX Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface Features Advanced Swit...
Datasheet PDF File KSZ8895MLX PDF File

KSZ8895MLX
KSZ8895MLX


Overview
KSZ8895MQX/RQX/FQX/MLX Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface Features Advanced Switch Features • IEEE 802.
1q VLAN Support for up to 128 Active VLAN Groups (Full-Range 4096 of VLAN IDs) • Static MAC Table Supports up to 32 Entries • VLAN ID Tag/Untagged Options, Per Port Basis • IEEE 802.
1p/q Tag Insertion or Removal on a Per Port Basis Based on Ingress Port (Egress) • Programmable Rate Limiting at the Ingress and Egress on a Per Port Basis • Jitter-Free Per Packet Based Rate Limiting Sup- port • Broadcast Storm Protection with Percentage Con- trol (Global and Per Port Basis) • IEEE 802.
1d Rapid Spanning Tree Protocol RSTP Support • Tail Tag Mode (1 Byte Added Before FCS) Sup- port at Port 5 to Inform the Processor Which Ingress Port Receives the Packet • 1.
4 Gbps High-Performance Memory Bandwidth and Shared Memory Based Switch Fabric with Fully Non-Blocking Configuration • Dual MII with MAC 5 and PHY 5 on Port 5, SW5MII/RMII for MAC 5 and P5-MII/RMII for PHY 5 • Enable/Disable Option for Huge Frame Size up to 2000 Bytes Per Frame • IGMP v1/v2 Snooping (IPv4) Support for Multicast Packet Filtering • IPv4/IPv6 QoS Support • Support Unknown Unicast/Multicast Address and Unknown VID Packet Filtering • Self-Address Filtering Comprehensive Configuration Register Access • Serial Management Interface (MDC/MDIO) to All PHYs Registers and SMI Interface (MDC/MDIO) to All Registers • High-Speed SPI (up to 25 MHz) and I2C Master Interface to all Internal Registers • I/O Pins Strapping and EEPROM to Program Selective Registers in Unmanaged Switch Mode • Control Registers Configurable on the Fly (PortPriority, 802.
1p/d/q, AN…) QoS/CoS Packet Prioritization Support • Per Port, 802.
1p and DiffServ-Based • 1/2/4-Queue QoS Prioritization Selection  2016 - 2021 Microchip Technology Inc.
• Programmable Weighted Fair Queuing for Ratio Control • Re-Mapping of 802.
1p Priority Field Per Port Basis Integrated 5-Port 10/100 Ethernet Switch • New Generati...


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