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AD1940

Analog Devices
Part Number AD1940
Manufacturer Analog Devices
Description SigmaDSP Multichannel 28-Bit Audio Processor
Published Mar 9, 2017
Detailed Description Anomaly Sheet for All Revisions SigmaDSP® Multichannel 28-Bit Audio Processor AD1940/AD1941 This anomaly list represen...
Datasheet PDF File AD1940 PDF File

AD1940
AD1940

Overview
Anomaly Sheet for All Revisions SigmaDSP® Multichannel 28-Bit Audio Processor AD1940/AD1941 This anomaly list represents the known bugs, anomalies, and workarounds for the AD1940 and AD1941 SigmaDSP products.
The anomalies listed apply to all AD1940/AD1941 packaged material branded as follows: First Line AD1940 or AD1941 Analog Devices, Inc.
is committed, through future silicon revisions, to continuously improving silicon functionality.
Analog Devices tries to ensure that these future silicon revisions remain compatible with your present software/systems implementing the recommended workarounds outlined here.
AD1940/AD1941 SILICON REVISION HISTORY Silicon Revision Identifier Kernel Revision Identifier Chip Marking All silicon branded AD1940YST AD1941YST Silicon Status Release Anomaly Sheet Rev.
0 No.
of Reported Anomalies 2 Rev.
0 Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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3113 © 2005 Analog Devices, Inc.
All rights reserved.
AD1940/AD1941 ANOMALIES 1.
Incorrect Polarity of Serial Input Port Left-Justified Mode [er001] Background: The input data format is set in the serial input control register.
Issue: When the AD1940/AD1941 serial input port is set to left-justified mode with left-justified formatted data being input to the part, the channels will be swapped.
This means that in the SigmaDSP core the left channel data is present when LRCLK is low, and the right channel data shows on the high half of the...


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