DatasheetsPDF.com

CY7C1372DV25

Part Number	CY7C1372DV25
Manufacturer	Cypress Semiconductor
Description	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Published	Mar 13, 2017
Detailed Description	CY7C1370DV25 CY7C1372DV25 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512K × 36/1M × 18...
Datasheet	CY7C1372DV25 PDF File

Overview

CY7C1370DV25 CY7C1372DV25 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 200-MHz bus operations with zero wait states ❐ Available speed grades are 200 and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte write capability ■ Single 2.
5 V core power supply (VDD) ■ 2.
5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.
0 ns (for 200-MHz device) ■ Clock enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ Available in JEDEC-standard Pb-free 100-pin TQFP, and non Pb-free 165-ball FBGA packages ■ IEEE 1149.
1 JTAG-compatible boundary scan ■ Burst capability – linear or interleaved burst order ■ “ZZ” sleep mode option and stop clock option Fun...

Similar Datasheet

CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM - Cypress Semiconductor

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)