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CY7C2268KV18

Part Number	CY7C2268KV18
Manufacturer	Cypress Semiconductor
Description	36-Mbit DDR II+ SRAM Two-Word Burst Architecture
Published	Mar 14, 2017
Detailed Description	CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit DD...
Datasheet	CY7C2268KV18 PDF File

Overview

CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.
5 Cycle Read Latency) with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.
5 Cycle Read Latency) with ODT Features ■ 36-Mbit density (2 M × 18, 1 M × 36) ■ 550 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.
5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ On-die termination (ODT) feature ❐ Supported for D[x:0], BWS[x:0], and K/K inputs ■ Synchronous internally self-timed writes ■ DDR II+ operates with 2.
5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW ■ Core VDD = 1.
8 V ± ...

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CY7C2268KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture - Cypress Semiconductor

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