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CY7C1314KV18

Part Number	CY7C1314KV18
Manufacturer	Cypress Semiconductor
Description	18-Mbit QDR II SRAM Two-Word Burst Architecture
Published	Mar 14, 2017
Detailed Description	CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architec...
Datasheet	CY7C1314KV18 PDF File

Overview

CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ QDR® II operates with 1.
5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to QDR I device with one cycle read latency when DOFF is asserted LOW ■ Available in × 18...

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CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture - Cypress Semiconductor

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