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CY7C1645KV18

Part Number	CY7C1645KV18
Manufacturer	Cypress Semiconductor
Description	144-Mbit QDR II+ SRAM Four-Word Burst Architecture
Published	Mar 14, 2017
Detailed Description	CY7C1643KV18/CY7C1645KV18 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit QDR® II...
Datasheet	CY7C1645KV18 PDF File

Overview

CY7C1643KV18/CY7C1645KV18 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.
0 Cycle Read Latency) 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.
0 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 450-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz ■ Available in 2.
0-clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Data valid pin (QVLD) to indicate valid...

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CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture - Cypress Semiconductor

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