DatasheetsPDF.com

CY7C25632KV18

Part Number	CY7C25632KV18
Manufacturer	Cypress Semiconductor
Description	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
Published	Mar 14, 2017
Detailed Description	CY7C25632KV18 CY7C25652KV18 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbi...
Datasheet	CY7C25632KV18 PDF File

Overview

CY7C25632KV18 CY7C25652KV18 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.
5 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.
5 Cycle Read Latency) with ODT Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 550 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.
5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Data valid pin (QVLD...

Similar Datasheet

CY7C25632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture - Cypress Semiconductor

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)