DatasheetsPDF.com

74AUP2G58

Part Number	74AUP2G58
Manufacturer	nexperia
Description	Low-power dual PCB configurable multiple function gate
Published	Sep 11, 2017
Detailed Description	74AUP2G58 Low-power dual PCB configurable multiple function gate Rev. 3 — 7 December 2020 Product data sheet 1. Gene...
Datasheet	74AUP2G58 PDF File

Overview

74AUP2G58 Low-power dual PCB configurable multiple function gate Rev.
3 — 7 December 2020 Product data sheet 1.
General description The 74AUP2G58 is a dual configurable multiple function gate with Schmitt-trigger inputs.
Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XOR, inverter and buffer; using the 3-bit input.
All inputs can be connected directly to VCC or GND.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.
8 V to 3.
6 V.
This device is fully specified for partial power down applications using IOFF.
The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
2.
Features and benefits • Wide supply voltage range from 0.
8 V to 3.
6 V • High noise immunity • ESD protection: • HBM JESD22-A114F exceeds 5000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Low static power consumption; ICC = 0.
9 μA (maximum) • Latch-up performance exceeds 100 mA per JESD 78 Class II • Inputs accept voltages up to 3.
6 V • Low noise overshoot and undershoot < 10 % of VCC • IOFF circuitry provides partial power-down mode operation • Specified from -40 °C to +85 °C and -40 °C to +125 °C Nexperia 74AUP2G58 Low-power dual PCB configurable multiple function gate 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range 74AUP2G58DP -40 °C to +125 °C 74AUP2G58GU -40 °C to +125 °C Name TSSOP10 XQFN10 Description plastic thin shrink small outline package; 10 leads; body width 3 mm plastic, extremely thin quad flat package; no leads; 10 terminals; body 1.
40 × 1.
80 × 0.
50 mm Version SOT552-1 SOT1160-1 4.
Marking Table 2.
Marking Type number 74AUP2G58DP 74AUP2G58GU Marking code[1] aK aK [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5.
Functional diagram nA nY nB nC Fig.
1.
Logic symbol (on...

Similar Datasheet

74AUP2G00 Low-power dual 2-input NAND gate - NXP
74AUP2G00 DUAL NAND GATE - Diodes
74AUP2G00 Low-power dual 2-input NAND gate - nexperia
74AUP2G00-Q100 Low-power dual 2-input NAND gate - nexperia
74AUP2G02 DUAL NOR GATE - Diodes
74AUP2G02 Low-power Dual 2-input NOR Gate - NXP
74AUP2G02 Low-power dual 2-input NOR gate - nexperia
74AUP2G04 Low-power dual inverter - NXP
74AUP2G04 DUAL INVERTERS - Diodes
74AUP2G04 Low-power dual inverter - nexperia

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)