DatasheetsPDF.com

74AUP2G00

NXP
Part Number 74AUP2G00
Manufacturer NXP
Description Low-power dual 2-input NAND gate
Published Jan 19, 2007
Detailed Description 74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 February 2013 Product data sheet 1. General description The 74AU...
Datasheet PDF File 74AUP2G00 PDF File

74AUP2G00
74AUP2G00

Overview
74AUP2G00 Low-power dual 2-input NAND gate Rev.
8 — 5 February 2013 Product data sheet 1.
General description The 74AUP2G00 provides dual 2-input NAND function.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.
8 V to 3.
6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.
8 V to 3.
6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
2.
Features and benefits  Wide supply voltage range from 0.
8 V to 3.
6 V  High noise immunity  Complies with JEDEC standards:  JESD8-12 (0.
8 V to 1.
3 V)  JESD8-11 (0.
9 V to 1.
65 V)  JESD8-7 (1.
2 V to 1.
95 V)  JESD8-5 (1.
8 V to 2.
7 V)  JESD8-B (2.
7 V to 3.
6 V)  ESD protection:  HBM JESD22-A114F Class 3A exceeds 5000 V  MM JESD22-A115-...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)