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BUK9614-30

NXP
Part Number BUK9614-30
Manufacturer NXP
Description TrenchMOS transistor Logic level FET
Published Mar 23, 2005
Detailed Description Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET GENERAL DESCRIPTION N-channel enhan...
Datasheet PDF File BUK9614-30 PDF File

BUK9614-30
BUK9614-30

Overview
Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting using ’trench’ technology.
The device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV.
It is intended for use in automotive and general purpose switching applications.
BUK9614-30 QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX.
30 69 125 175 14 UNIT V A W ˚C mΩ PINNING - SOT404 PIN 1 2 3 mb gate drain source drain DESCRIPTION PIN CONFIGURATION mb SYMBOL d g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN.
- 55 MAX.
30 30 10 69 48 240 125 175 UNIT V V V A A A W ˚C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS minimum footprint, FR4 board TYP.
50 MAX.
1.
2 UNIT K/W K/W ESD LIMITING VALUE SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model (100 pF, 1.
5 kΩ) MIN.
MAX.
2 UNIT kV December 1997 1 Rev 1.
100 Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS ±V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Gate-source breakdown voltag...


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