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MT49H16M36

Part Number	MT49H16M36
Manufacturer	Micron
Description	576Mb CIO Reduced Latency
Published	Dec 7, 2017
Detailed Description	576Mb: x9 x18 x36 CIO RLDRAM 2 Features CIO RLDRAM 2 MT49H64M9 – 64 Meg x 9 x 8 Banks MT49H32M18 – 32 Meg x 18 x 8 Bank...
Datasheet	MT49H16M36 PDF File

Overview

576Mb: x9 x18 x36 CIO RLDRAM 2 Features CIO RLDRAM 2 MT49H64M9 – 64 Meg x 9 x 8 Banks MT49H32M18 – 32 Meg x 18 x 8 Banks MT49H16M36 – 16 Meg x 36 x 8 Banks Features • 533 MHz DDR operation (1.
067 Gb/s/pin data rate) • 38.
4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • Organization – 64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O – 8 banks • Reduced cycle time (15ns at 533 MHz) • Nonmultiplexed addresses (address multiplexing option available) • SRAM-type interface • Programmable READ latency (RL), row cycle time, and burst sequence length • Balanced READ and WRITE latencies in order to optimize data bus utilization • Data mask for WRITE commands • Differential input clocks (CK, CK#) • Differential input data clocks (DKx, DKx#) • On-die DLL generates CK edge-aligned data and output data clock signals • Data valid signal (QVLD) • 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms) • HSTL I/O (1.
...

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