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BS62LV4001

Part Number	BS62LV4001
Manufacturer	Brilliance Semiconductor
Description	Low Power/Voltage CMOS SRAM 512K X 8 bit
Published	Mar 23, 2005
Detailed Description	BSI FEATURES Low Power/Voltage CMOS SRAM 512K X 8 bit GENERAL DESCRIPTION BS62LV4001 • Wide Vcc operation voltage...
Datasheet	BS62LV4001 PDF File

Overview

BSI FEATURES Low Power/Voltage CMOS SRAM 512K X 8 bit GENERAL DESCRIPTION BS62LV4001 • Wide Vcc operation voltage : 2.
4V ~ 5.
5V • Low power consumption Vcc = 3.
0V C-grade: 20mA (Max.
) operating current I -grade: 25mA (Max.
) operating current 0.
25uA (Typ.
) CMOS standby current Vcc = 5.
0V C-grade: 45mA (Max.
) operation current I -grade: 50mA (Max.
) operating current 1.
5uA (Typ.
) CMOS standby current • High speed access time : -70 70ns (Max.
) at Vcc = 3.
0V -10 100ns (Max.
) at Vcc = 3.
0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.
5V • Easy expansion with CE and OE options The BS62LV4001 is a high performance, low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 2.
4V to 5.
5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speed and low power features with maximum access time of 70/ 100ns in 3.
0V operation.
Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers.
The BS62LV4001 has an automatic power down feature, reducing the power consumption significantly when chip is deselected.
The BS62LV4001 is available in DICE form, JEDEC standard 32 pin SOP, 32 pin TSOPII, 32 pin TSOP and 32 pin Small SOP.
PRODUCT FAMILY PIN CONFIGURATIONS A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 BS62LV4001SC 9 BS62LV4001SI 10 BS62LV4001EC BS62LV4001EI 11 BS62LV4001PC 12 BS62LV4001PI 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 FUNCTIONAL BLOCK DIAGRAM A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4 • Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 X 2048 2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 256 Column Decoder 16 CE WE OE Vdd Gnd ...

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