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IDCS3

AMI
Part Number IDCS3
Manufacturer AMI
Description CMOS Gate Array
Published Mar 12, 2018
Detailed Description ,'&6 ® $0,+*  PLFURQ &026 *DWH $UUD\ Description IDCS3 is a non-inverting, CMOS-level Schmitt trigger input buffe...
Datasheet PDF File IDCS3 PDF File

IDCS3
IDCS3

Overview
,'&6 ® $0,+*  PLFURQ &026 *DWH $UUD\ Description IDCS3 is a non-inverting, CMOS-level Schmitt trigger input buffer piece with voltage hysteresis.
Logic Symbol Truth Table Pin Loading IDCS3 QC P PADM D PADM QC LL HH Load PADM 4.
90 pF HDL Syntax Verilog IDCS3 inst_name (QC, PADM); VHDL.
.
inst_name: IDCS3 port map (QC, PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation.
Value TBD 17.
0 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.
0V, Typical Process Delay (ns) From To Parameter 1 PADM QC tPLH tPHL 1.
37 1.
01 Delay will vary with input conditions.
See page 2-...


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