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ODCSXE12

Part Number	ODCSXE12
Manufacturer	AMI
Description	CMOS Gate Array
Published	Mar 12, 2018
Detailed Description	2'&6;([[ ® $0,+* PLFURQ &026 *DWH $UUD\ Description ODCSXExx is a family of 4 to 16 mA, non-inverting, CMOS-level...
Datasheet	ODCSXE12 PDF File

Overview

2'&6;([[ ® $0,+* PLFURQ &026 *DWH $UUD\ Description ODCSXExx is a family of 4 to 16 mA, non-inverting, CMOS-level, tristate output buffer pieces with active low enables and controlled slew rate outputs.
Logic Symbol Truth Table ODCSXExx EN SL A PADM EN A PADM LL L LH H HX Z HDL Syntax Verilog ODCSXExx inst_name (PADM, A, EN); VHDL.
.
inst_name: ODCSXExx port map (PADM, A, EN); Pin Loading Pin Name A (eq-load) EN (eq-load) PADM (pF) ODCSXE04 2.
3 6.
9 4.
94 Power Characteristics Cell Output Drive (mA) ODCSXE04 4 ODCSXE08 8 ODCSXE12 12 ODCSXE16 16 a.
See page 2-15 for power equation.
ODCSXE08 2.
3 6.
9 4.
94 Load ODCSXE12 2.
3...

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