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ODCSXX04

AMI
Part Number ODCSXX04
Manufacturer AMI
Description CMOS Gate Array
Published Mar 12, 2018
Detailed Description 2'&6;;[[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description ODCSXXxx is a family of 4 to 24 mA, non-inverting, CMOS-level...
Datasheet PDF File ODCSXX04 PDF File

ODCSXX04
ODCSXX04

Overview
2'&6;;[[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description ODCSXXxx is a family of 4 to 24 mA, non-inverting, CMOS-level, output buffer pieces with controlled slew rate outputs.
Logic Symbol Truth Table ODCSXXxx SL A PADM A PADM LL HH HDL Syntax Verilog ODCSXXxx inst_name (PADM, A); VHDL.
.
inst_name: ODCSXXxx port map (PADM, A); Pin Loading Pin Name A (eq-load) ODCSXX04 9.
3 Power Characteristics Cell Output Drive (mA) ODCSXX04 4 ODCSXX08 8 ODCSXX12 12 ODCSXX16 16 ODCSXX24 24 a.
See page 2-15 for power equation.
ODCSXX08 9.
3 Load ODCSXX12 9.
3 ODCSXX16 9.
3 Power Characteristicsa Static IDD (TJ = 85°C) (nA) TBD EQLpd (Eq-load) 198.
6 TBD 220.
0 TBD 240.
8 TBD 263.
6 TBD 282.
3 ODCSXX24 11.
4 Pad Logic 4-19 2'&6;;[[ $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.
0V, Typical Process Capacitive Load (pF) 15 ODCSXX04 From: A tPLH To: PADM tPHL 2.
46 2.
44 Capacitive ...


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