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ODTHXE24

Part Number	ODTHXE24
Manufacturer	AMI
Description	CMOS Gate Array
Published	Mar 12, 2018
Detailed Description	2'7+;( ® $0,+* PLFURQ &026 *DWH $UUD\ Description ODTHXE24 is a high performance, 24 mA, non-inverting, TTL-le...
Datasheet	ODTHXE24 PDF File

Overview

2'7+;( ® $0,+* PLFURQ &026 *DWH $UUD\ Description ODTHXE24 is a high performance, 24 mA, non-inverting, TTL-level, tristate output buffer piece with active low enable.
Logic Symbol Truth Table Pin Loading ODTHXE24 EN A PADM EN A PADM LL L LH H HX Z A EN PADM Load 3.
5 eql 6.
5 eql 4.
93 pF HDL Syntax Verilog ODTHXE24 inst_name (PADM, A, EN); VHDL.
.
inst_name: ODTHXE24 port map (PADM, A, EN); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation.
Value TBD 297.
0 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.
0V, Typical Process Delay (ns) From To Parameter 15 A PADM tPLH tPHL 0.
89 1.
19 tHZ 1.
06 EN PADM tLZ tZH 1.
02 0.
70 tZL 1.
10 Delay will vary with input conditions.
See page 2-17 for interconnect estimates.
50 1.
17 1.
64 0.
96 1.
59 Capacitive Load (pF) 100 1.
55 2.
30 1.
32 2.
27 200 2.
26 3.
60 2.
03 3.
59 300 (max) 2.
94 4.
91 2.
74 4.
88 Pad Logic 4-...

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ODTHXE24 CMOS Gate Array - AMI

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