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M13D64322A

Part Number	M13D64322A
Manufacturer	ESMT
Description	Low Power DDR SDRAM
Published	Sep 20, 2018
Detailed Description	ESMT LPDDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cyc...
Datasheet	M13D64322A PDF File

Overview

ESMT LPDDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 16 & full page Special function support - DS (Drive Strength) - Deep Power Down Mode (DPD Mode) M13D64322A (2S) 512K x 32 Bit x 4 Banks Low Power DDR SDRAM All inputs except data & DM are sampled at the rising edge of the system clock(CLK) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only VDD = 1...

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M13D64322A Low Power DDR SDRAM - ESMT

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