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MR45V100A

LAPIS
Part Number MR45V100A
Manufacturer LAPIS
Description 1M-Bit EdRAM
Published May 5, 2019
Detailed Description MR45V100A FEDR45V100A-02 Issue Date: Oct. 09, 2018 1M Bit(131,072-Word  8-Bit) FeRAM (Ferroelectric Random Access Mem...
Datasheet PDF File MR45V100A PDF File

MR45V100A
MR45V100A

Overview
MR45V100A FEDR45V100A-02 Issue Date: Oct.
09, 2018 1M Bit(131,072-Word  8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI GENERAL DESCRIPTION The MR45V100A is a nonvolatile 128Kword x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology.
The MR45V100A is accessed using Serial Peripheral Interface.
Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required to hold data.
This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs.
Therefore, the write cycle time can be equal to the read cycle time and the power consumption duri...


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