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MR44V100A

LAPIS
Part Number MR44V100A
Manufacturer LAPIS
Description 1M-Bit FeRAM
Published May 5, 2019
Detailed Description MR44V100A FEDR44V100A-02 Issue Date: Oct. 25, 2018 1M Bit(131,072-Word -Word  8-Bit) FeRAM (Ferroelectric Random Acce...
Datasheet PDF File MR44V100A PDF File

MR44V100A
MR44V100A

Overview
MR44V100A FEDR44V100A-02 Issue Date: Oct.
25, 2018 1M Bit(131,072-Word -Word  8-Bit) FeRAM (Ferroelectric Random Access Memory) I2C GENERAL DESCRIPTION The MR44V100A is a nonvolatile 131,072-word x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology.
The MR44V100A is accessed using Two-wire Serial Interface ( I2C BUS ).
Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required to hold data.
This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs.
Therefore, the write cycle time can be equal to the read cycle time and the pow...


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