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MR45V200B

LAPIS
Part Number MR45V200B
Manufacturer LAPIS
Description FeRAM
Published May 5, 2019
Detailed Description MR45V200B FEDR45V200B-02 Issue Date: Oct. 2, 2018 2M(262,144-Word  8-Bit) FeRAM (Ferroelectric Random Access Memory) ...
Datasheet PDF File MR45V200B PDF File

MR45V200B
MR45V200B

Overview
MR45V200B FEDR45V200B-02 Issue Date: Oct.
2, 2018 2M(262,144-Word  8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI GENERAL DESCRIPTION The MR45V200B is a nonvolatile 262,144-word x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology.
The MR45V200B is accessed using Serial Peripheral Interface.
Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required to hold data.
This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs.
Therefore, the write cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly.
The MR45V200B can be used in various applications, because the device is guaranteed for the write/read tolerance of 1013 cycles per bit and the rewrite count can be extended significantly.
FEATURES • 262,144-word  8-bit configuration (Serial Periphera...


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