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74AHC02

nexperia
Part Number 74AHC02
Manufacturer nexperia
Description Quad 2-input NOR gate
Published Jul 23, 2019
Detailed Description 74AHC02; 74AHCT02 Quad 2-input NOR gate Rev. 5 — 11 May 2020 Product data sheet 1. General description The 74AHC02; 74...
Datasheet PDF File 74AHC02 PDF File

74AHC02
74AHC02

Overview
74AHC02; 74AHCT02 Quad 2-input NOR gate Rev.
5 — 11 May 2020 Product data sheet 1.
General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard No.
7-A.
The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
2.
Features and benefits • Balanced propagation delays • All inputs have a Schmitt-trigger action • Inputs accept voltages higher than VCC • Input levels: • For 74AHC02: CMOS level • For 74AHCT02: TTL level • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V • CDM EIA/JESD22-C101C exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name 74AHC02D -40 °C to +125 °C SO14 74AHCT02D 74AHC02PW -40 °C to +125 °C TSSOP14 74AHCT02PW 74AHC02BQ -40 °C to +125 °C DHVQFN14 74AHCT02BQ Description plastic small outline package; 14 leads; body width 3.
9 mm plastic thin shrink small outline package; 14 leads; body width 4.
4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5 × 3 × 0.
85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4.
Functional diagram 2 1A 3 1B 5 2A 6 2B 8 3A 9 3B 11 4A 12 4B 1Y 1 2Y 4 3Y 10 4Y 13 mna216 Fig.
1.
Logic symbol 2 ≥1 3 1 5 ≥1 6 4 8 ≥1 9 10 11 ≥1 12 13 001aah084 Fig.
2.
IEC logic symbol 5.
Pinning information 74AHC02; 74AHCT02 Quad 2-input NOR gate A Y B mna215 Fig.
3.
Logic diagram (one gate) 5.
1.
Pinning 1Y 1 1A 2 1B 3 2Y 4 2A 5 2B 6 GND 7 14 VCC 13 4Y 12 4B 02 11 4A 10 3Y 9 3B 8 3A 001aac919 Fig.
4.
Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) 1 1Y 14 VCC terminal 1 index area 1A 2 1B 3 2Y 4 2A 5 2B 6 02 GND(1) 13 4Y 12 4B 11 4A 10 3Y 9 3B GND 7 3A 8 001aac920 Fig.
5.
Transparent top view (1) This is not a gr...


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