DatasheetsPDF.com

74ALVC16836A

nexperia
Part Number 74ALVC16836A
Manufacturer nexperia
Description 20-bit registered driver
Published Jul 23, 2019
Detailed Description 74ALVC16836A 20-bit registered driver with inverted register enable; 3-state Rev. 2 — 12 September 2018 Product data ...
Datasheet PDF File 74ALVC16836A PDF File

74ALVC16836A
74ALVC16836A

Overview
74ALVC16836A 20-bit registered driver with inverted register enable; 3-state Rev.
2 — 12 September 2018 Product data sheet 1.
General description The 74ALVC16836A is a 20-bit universal bus driver.
Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent.
When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flipflop.
When OE is LOW the outputs are active.
When OE is HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
2.
Features and benefits • Wide supply voltage range from 1.
2 V to 3.
6 V • CMOS low-power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.
0 V • MULTIBYTE flow-through standard pin-out architecture • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • Output drive capability 50 Ω transmission lines at 85°C • Input diodes to accommodate strong drivers • Complies with JEDEC standard no.
8-1A • Complies with JEDEC standards: • JESD8-5 (2.
3 V to 2.
7 V) • JESD8B/JESD36 (2.
7 V to 3.
6 V) • ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V • CDM JESD22-C101E exceeds 1000 V 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range 74ALVC16836ADGG −40 °C to +85 °C Name TSSOP56 Description Version plastic thin shrink small outline package; 56 leads; SOT364-1 body width 6.
1 mm Nexperia 4.
Functional diagram OE CP LE A1 D LE CP Fig.
1.
Logic diagram 74ALVC16836A 20-bit registered driver with inverted register enable; 3-state Y1 aaa-026917 OE 1 CP 56 LE 29 A1 55 A2 54 A3 52 A4 51 ...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)