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74HCT2G00-Q100

nexperia
Part Number 74HCT2G00-Q100
Manufacturer nexperia
Description Dual 2-input NAND gate
Published Jul 29, 2019
Detailed Description 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate Rev. 2 — 20 November 2018 Product data sheet 1. General descripti...
Datasheet PDF File 74HCT2G00-Q100 PDF File

74HCT2G00-Q100
74HCT2G00-Q100

Overview
74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate Rev.
2 — 20 November 2018 Product data sheet 1.
General description The 74HC2G00-Q100; 74HCT2G00-Q100 is a dual 2-input NAND gate.
Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2.
Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide supply voltage range from 2.
0 V to 6.
0 V • Input levels: • For 74HC2G00-Q100: CMOS level • For 74HCT2G00-Q100: TTL level • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω) 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name 74HC2G00DP-Q100 -40 °C to +125 °C TSSOP8 74HCT2G00DP-Q100 74HC2G00DC-Q100 -40 °C to +125 °C VSSOP8 74HCT2G00DC-Q100 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.
5 mm Version SOT505-2 plastic very thin shrink small outline package; SOT765-1 8 leads; body width 2.
3 mm Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate 4.
Marking Table 2.
Marking code Type number 74HC2G00DP-Q100 74HCT2G00DP-Q100 74HC2G00DC-Q100 74HCT2G00DC-Q100 Marking code[1] H00 T00 H00 T00 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5.
Functional diagram 1 1A 2 1B 5 2A 6 2B 1Y 7 2Y 3 mna712 Fig.
1.
Logic symbol 1& 2 7 5& 6 3 mna713 Fig.
2.
IEC logic symbol B Y A mna099 Fig.
3.
Logic diagram (one driver) 6.
Pinning information 6.
1.
Pinning 74HC2G00 74HCT2G00 1A 1B ...


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