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HEF4043B-Q100

Part Number	HEF4043B-Q100
Manufacturer	nexperia
Description	Quad R/S latch
Published	Jul 29, 2019
Detailed Description	HEF4043B-Q100 Quad R/S latch with 3-state outputs Rev. 3 — 8 December 2021 Product data sheet 1. General description T...
Datasheet	HEF4043B-Q100 PDF File

Overview

HEF4043B-Q100 Quad R/S latch with 3-state outputs Rev.
3 — 8 December 2021 Product data sheet 1.
General description The HEF4043B-Q100 is a quad R/S latch with 3-state outputs and common output enable input (OE).
Each latch has set (nS), and reset (nR) inputs and a 3-state output (nQ).
When OE is LOW, the latch outputs are in the high impedance OFF-state.
OE does not affect the state of the latch.
Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications.
2.
Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 3) • Specified from -40 °C to +85 °C • Wide supply voltage range from 3.
0 to 15.
0 V • CMOS low power dissipation • High noise immunity • Fully static operation • 5 V, 10 V, and 15 V parametric ratings • Standardized symmetrical output characteristics • Complies with JEDEC standard JESD 13-B • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) 3.
Applications • Four-bit storage with output enable 4.
Ordering information Table 1.
Ordering information Type number Package Temperature range HEF4043BT-Q100 -40 °C to +85 °C Name SO16 Description Version plastic small outline package; 16 leads; SOT109-1 body width 3.
9 mm Nexperia 5.
Functional diagram HEF4043B-Q100 Quad R/S latch with 3-state outputs 4 1S 3 1R 1Q 2 6 2S 7 2R 12 3S 11 3R 2Q 9 3-STATE OUTPUTS 3Q 10 14 4S 15 4R 5 OE Fig.
1.
Functional diagram 4Q 1 001aae616 6.
Pinning information nS nQ nR OE to other latches 001aae618 Fig.
2.
Logic diagram for one latch 6.
1.
Pinning HEF4043B 4Q 1 1Q 2 1R 3 1S 4 OE 5 2S 6 2R 7 VSS 8 Fig.
3.
Pin configuration SOT109-1 (SO16) 16 VDD 15 4R 14 4S 13 n.
c.
12 3S 11 3R 10 3Q 9 2Q 001aae617 HEF40...

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HEF4043B-Q100 Quad R/S latch - nexperia

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