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74ACT11138

Texas Instruments
Part Number 74ACT11138
Manufacturer Texas Instruments
Description 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
Published Aug 17, 2019
Detailed Description 54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993 • ...
Datasheet PDF File 74ACT11138 PDF File

74ACT11138
74ACT11138

Overview
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993 • Designed Specifically for High-Speed 54ACT11138 .
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J PACKAGE Memory Decoders and Data Transmission 74ACT11138 .
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D, N, OR PW PACKAGE Systems (TOP VIEW) • Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise t• EPIC (Enhanced-Performance Implanted Y1 Y2 Y3 GND Y4 Y5 Y6 1 2 3 4 5 6 7 16 Y0 15 A 14 B 13 C 12 VCC 11 G1 10 G2A CMOS) 1-mm Process Y7 8 9 G2B • 650-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic Small-Outline Packages, Plastic Thin 54ACT11138 .
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FK PACKAGE (TOP VIEW) B C NC VCC G1 Shrink Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 3 2 1 20 19 A4 18 G2A description Y0 5 17 G2B The ′ACT11138 circuit is designed to be used in high-performance memory-decoding or datarouting applications requiring very short NC 6 16 NC Y1 7 15 Y7 Y2 8 14 9 10 11 12 13 Y6 propagation delay times.
In high-performance Y3 GND NC Y4 Y5 memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories utilizing a NC – No internal connection fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory.
This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the three enable inputs select one of eight input lines.
Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter.
An enable input can be used as a data input for ...


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