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TMS320TCI100

Texas Instruments
Part Number TMS320TCI100
Manufacturer Texas Instruments
Description DIGITAL SIGNAL PROCESSOR
Published Sep 7, 2019
Detailed Description TMS320TCI100 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS218I − MAY 2003 − REVISED APRIL 2009 D Highest-Performance Fixed...
Datasheet PDF File TMS320TCI100 PDF File

TMS320TCI100
TMS320TCI100

Overview
TMS320TCI100 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS218I − MAY 2003 − REVISED APRIL 2009 D Highest-Performance Fixed-Point Digital − 8M-Bit (1024K-Byte) L2 Unified Mapped Signal Processors (DSPs) RAM/Cache (Flexible Allocation) − 1.
67-, 1.
39-ns Instruction Cycle Time − 600-, 720-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − Twenty-Eight Operations/Cycle − 4800, 5760 MIPS − Fully Software-Compatible With C62x − TCI100/C6416 Pin-Compatible − Extended Temperature Devices Available D VelociTI.
2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core − Eight Highly Independent Functional Units With VelociTI.
2 Extensions: − Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle − Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle − Non-Aligned Load-Store Architecture − 64 32-Bit General-Purpose Registers D Two External Memory Interfaces (EMIFs) − One 64-Bit (EMIFA), One 16-Bit (EMIFB) − Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) − 1280M-Byte Total Addressable External Memory Space D Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) D Host-Port Interface (HPI) − User-Configurable Bus Width (32-/16-Bit) D 32-Bit/33-MHz, 3.
3-V PCI Master/Slave Interface Conforms to PCI Specification 2.
2 − Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O − Four-Wire Serial EEPROM Interface − PCI Interrupt Request Under DSP Program Control − DSP Interrupt Via PCI I/O Cycle D Three Multichannel Buffered Serial Ports − Instruction Packing Reduces Code Size − Direct Interface to T1/E1, MVIP, SCSA − All Instructions Conditional Framers D Instruction Set Features − Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − ...


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