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LMK61E0M

Texas Instruments
Part Number LMK61E0M
Manufacturer Texas Instruments
Description Ultra-Low Jitter Programmable Oscillator
Published Sep 27, 2019
Detailed Description Product Folder Order Now Technical Documents Tools & Software Support & Community LMK61E0M SNAS692A – JANUARY 2017 ...
Datasheet PDF File LMK61E0M PDF File

LMK61E0M
LMK61E0M

Overview
Product Folder Order Now Technical Documents Tools & Software Support & Community LMK61E0M SNAS692A – JANUARY 2017 – REVISED MAY 2017 LMK61E0M Ultra-Low Jitter Programmable Oscillator With Internal EEPROM 1 Features •1 Ultra-Low Noise, High Performance – Jitter: 500-fs RMS Typical fOUT > 50 MHz on LMK61E0M • LMK61E0M Supports 3.
3-V LVCMOS Output up to 200 MHz • Total Frequency Tolerance of ±25 ppm • System Level Features – Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal – Internal EEPROM: User Configurable Start-Up Settings • Other Features – Device Control: Fast Mode I2C up to 1000 kHz – 3.
3-V Operating Voltage – Industrial Temperature Range (–40ºC to +85ºC) – 7-mm × 5-mm 8-Pin Package • Default Frequency: 70.
656 MHz 2 Applications • High-Performance Replacement for Crystal, SAW, or Silicon-Based Oscillators • Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN • Test and Measurement • Medical Imaging • FPGA, Processor Attach • xDSL, Broadcast Video 3 Description The LMK61E0 family of ultra-low jitter PLLatinumTM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks.
The LMK61E0M supports 3.
3-V LVCMOS outputs.
The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface.
The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.
5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.
2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements.
The frequency margining features ...


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