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AS4C128M16D3LA-12BIN

Alliance Semiconductor
Part Number AS4C128M16D3LA-12BIN
Manufacturer Alliance Semiconductor
Description 128M x 16 bit DDR3L Synchronous DRAM
Published Oct 13, 2019
Detailed Description AS4C128M16D3LA-12BIN Revision History 2Gb AS4C128M16D3LA-12BIN - 96 ball FBGA PACKAGE Revision Details Rev 1.0 Prelimin...
Datasheet PDF File AS4C128M16D3LA-12BIN PDF File

AS4C128M16D3LA-12BIN
AS4C128M16D3LA-12BIN

Overview
AS4C128M16D3LA-12BIN Revision History 2Gb AS4C128M16D3LA-12BIN - 96 ball FBGA PACKAGE Revision Details Rev 1.
0 Preliminary datasheet Date May.
2016 Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc.
reserves the right to change products or specification without notice Confidential -183- Rev.
1.
0 May 2016 AS4C128M16D3LA-12BIN 128M x 16 bit DDR3L Synchronous DRAM (SDRAM) Features • JEDEC Standard Compliant • Power supplies: VDD & VDDQ = 1.
35V • Backward compatible to VDD & VDDQ = 1.
5V ±0.
075V • Industrial temperature: TC = -40~95°C • Supports JEDEC clock jitter specification • Fully synchronous operation • Fast clock rate: 800MHz • Differential Clock, CK & CK# • Bidirectional differential data strobe - DQS & DQS# • 8 internal banks for concurrent operation • 8n-bit prefetch architecture • Pipelined internal architecture • Precharge & active power down • Programmable Mode & Extended Mode registers • Additive Latency (AL): 0, CL-1, CL-2 • Programmable Burst lengths: 4, 8 • Burst type: Sequential / Interleave • Output Driver Impedance Control • 8192 refresh cycles / 64ms - Average refresh period 7.
8µs @ -40°C TC +85°C 3.
9µs @ +85°C TC +95°C • Write Leveling • ZQ Calibration • Dynamic ODT (Rtt_Nom & Rtt_WR) • RoHS compliant • Auto Refresh and Self Refresh • 96-ball 8 x 13 x 1.
0mm FBGA package - Pb and Halogen Free Overview The 2Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation.
It is internally configured as an eight bank DRAM.
The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices.
These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differenti...


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