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AS4C1M16S-C

Alliance Memory
Part Number AS4C1M16S-C
Manufacturer Alliance Memory
Description 1M x 16 bit Synchronous DRAM
Published Oct 13, 2019
Detailed Description Revision History Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Add 166MHZ and commercial & industrial parts. ...
Datasheet PDF File AS4C1M16S-C PDF File

AS4C1M16S-C
AS4C1M16S-C

Overview
Revision History Revision Rev 1.
0 Rev 2.
0 Details Preliminary datasheet Add 166MHZ and commercial & industrial parts.
AS4C1M16S-C&I Date February 2015 March 2015 Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc.
reserves the right to change products or specification without notice.
Confidential 0 Rev.
2.
0 March /2015 AS4C1M16S-C&I 1M x 16 bit Synchronous DRAM (SDRAM) Advanced (Rev.
2.
0, March /2015) Features  Fast access time: 5.
4/5.
4ns  Fast clock rate: 166/143 MHz  Self refresh mode: standard  Internal pipelined architecture  512K word x 16-bit x 2-bank  Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function  Individual byte controlled by LDQM and UDQM  Auto Refresh and Self Refresh  4096 refresh cycles/64ms  CKE power down mode  Industrial Temperature: -40~85°C  JEDEC standard +3.
3V0.
3V power supply  Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C)  Interface: LVTTL  50-pin 400 mil plastic TSOP II package -Pb and Halogen Free Overview The 16Mb SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits.
It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).
Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option.
An auto precharge function may be enabled to provide a self-timed row precharge that is ini...


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