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ADSP-21061L

Analog Devices
Part Number ADSP-21061L
Manufacturer Analog Devices
Description Commercial Grade SHARC DSP Microcomputer
Published Oct 30, 2019
Detailed Description a SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Archite...
Datasheet PDF File ADSP-21061L PDF File

ADSP-21061L
ADSP-21061L

Overview
a SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing features KEY FEATURES—PROCESSOR CORE 50 MIPS, 20 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Commercial Grade SHARC DSP Microcomputer ADSP-21061/ADSP-21061L Dual data address generators with modulo and bit-reverse addressing Efficient program sequencing with zero-overhead looping: single-cycle loop setup IEEE JTAG Standard 1149.
1 test access port and on-chip emulation 32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format 240-lead MQFP package, thermally enhanced MQFP, 225-ball plastic ball grid array (PBGA) Lead (Pb) free packages.
For more information, see Ordering Guide on Page 52.
CORE PROCESSOR TIMER INSTRUCTION CACHE 32 ϫ 48-BIT DAG1 DAG2 8 ϫ 4 ϫ 32 8 ϫ 4 ϫ 24 PROGRAM SEQUENCER PM ADDRESS BUS DM ADDRESS BUS 24 32 BUS CONNECT (PX) PM DATA BUS 48 DM DATA BUS 40/32 DUAL-PORTED SRAM TWO INDEPENDENT DUAL-PORTED BLOCKS PROCESSOR PORT I/O PORT ADDR DATA DATA ADDR ADDR DATA DATA ADDR IOD IOA 48 17 S B LOCK 0 BLOCK 1 JTAG TEST AND EMULATION 7 EXTERNAL PORT ADDR BUS MUX 32 MULTIPROCESSOR INTERFACE DATA BUS MUX 48 HOST PORT DATA REGISTER FILE MULT 16 ϫ 40-BIT BARREL SHIFTER ALU IOP REGISTERS (MEMORY MAPPED) CONTROL, STATUS AND DATA BUFFERS DMA CONTROLLER SERIAL PORTS (2) 4 6 6 I/O PROCESSOR Figure 1.
Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev.
D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable.
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