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EP1K100

Altera
Part Number EP1K100
Manufacturer Altera
Description Programmable Logic Device
Published Nov 11, 2019
Detailed Description May 2003, ver. 3.4 ACEX 1K Programmable Logic Device Family ® Data Sheet Features... ■ Programmable logic devices (PL...
Datasheet PDF File EP1K100 PDF File

EP1K100
EP1K100

Overview
May 2003, ver.
3.
4 ACEX 1K Programmable Logic Device Family ® Data Sheet Features.
.
.
■ Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – Dual-port capability with up to 16-bit width per embedded array block (EAB) – Logic array for general logic functions ■ High density – 10,000 to 100,000 typical gates (see Table 1) – Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity) ■ Cost-efficient programmable architecture for high-volume applications – Cost-optimized process – Low cost solution for high-performance communications applications ■ System-level features – MultiVoltTM I/O pins can drive or be driven by 2.
5-V, 3.
3-V, or 5.
0-V devices – Low power consumption – Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.
2 for 3.
3-V operation at 33 MHz or 66 MHz ■ Extended temperature range Table 1.
ACEXTM 1K Device Features Feature Typical gates Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins EP1K10 10,000 56,000 576 3 12,288 136 EP1K30 30,000 119,000 1,728 6 24,576 171 EP1K50 50,000 199,000 2,880 10 40,960 249 EP1K100 100,000 257,000 4,992 12 49,152 333 Tools 13 Altera Corporation DS-ACEX-3.
4 1 ACEX 1K Programmable Logic Device Family Data Sheet .
.
.
and More Features – -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.
2 for 5.
0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std.
1149.
1-1990, available without consuming additional device logic.
– Operate with a 2.
5-V internal supply voltage – In-circuit reconfigurability (ICR) v...


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