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UC1825-SP

Texas Instruments
Part Number UC1825-SP
Manufacturer Texas Instruments
Description HIGH-SPEED PWM CONTROLLER
Published Jan 16, 2020
Detailed Description UC1825-SP www.ti.com SLUS870A – JANUARY 2009 – REVISED MARCH 2012 RAD-TOLERANT CLASS V, HIGH-SPEED PWM CONTROLLER Che...
Datasheet PDF File UC1825-SP PDF File

UC1825-SP
UC1825-SP

Overview
UC1825-SP www.
ti.
com SLUS870A – JANUARY 2009 – REVISED MARCH 2012 RAD-TOLERANT CLASS V, HIGH-SPEED PWM CONTROLLER Check for Samples: UC1825-SP FEATURES 1 • QML-V Qualified, SMD 5962-87681 • Rad-Tolerant: 30 kRad (Si) TID (1) • Compatible With Voltage- or Current-Mode Topologies • Practical Operation Switching Frequencies to 1 MHz • 50-ns Propagation Delay-to-Output • High-Current Dual Totem Pole Outputs (1.
5 A Peak) • Wide Bandwidth Error Amplifier • Fully Latched Logic With Double-Pulse Suppression • Pulse-by-Pulse Current Limiting • Soft Start/Maximum Duty-Cycle Control • Undervoltage Lockout With Hysteresis • Low Start-Up Current (1.
1 mA) (1) Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec.
Radiation Lot Acceptance Testing is available - contact factory for details.
DESCRIPTION The UC1825 PWM control device is optimized for high-frequency switched mode power supply applications.
Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier.
This controller is designed for use in either current-mode or voltage mode systems with the capability for input voltage feedforward.
Protection circuitry includes a current limit comparator with a 1-V threshold, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty-cycle clamp.
The logic is fully latched to provide jitter-free operation and prohibit multiple pulses at an output.
An undervoltage lockout section with 800 mV of hysteresis assures low start up current.
During undervoltage lockout, the outputs are high impedance.
This device features totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET.
The on state is designed as a high level.
Figure 1.
BLOCK DIAGRAM CLOCK 4 RT 5 CT 6 RAMP 7 E/A Out 3 Error Amp NI 2 INV 1 1.
25 V OSC Wide Bandwidth Erro...


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