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PSoC4100PS

Cypress
Part Number PSoC4100PS
Manufacturer Cypress
Description Programmable System-on-Chip
Published Jan 19, 2020
Detailed Description PSoC® 4: PSoC 4100PS Datasheet Programmable System-on-Chip (PSoC®) General Description Cypress' PSoC® 4 is a scalable a...
Datasheet PDF File PSoC4100PS PDF File

PSoC4100PS
PSoC4100PS

Overview
PSoC® 4: PSoC 4100PS Datasheet Programmable System-on-Chip (PSoC®) General Description Cypress' PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex™-M0+ CPU.
It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
PSoC 4100PS is a member of the PSoC 4 platform architecture.
It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.
Features Programmable Analog Blocks ■ Two dedicated analog-to-digital converters (ADC) including a 12-bit SAR ADC and a 10-bit single-slope ADC ■ Four opamps, two low-power comparators, and a flexible 38-channel analog mux to create custom Analog Front Ends (AFE) ■ Two 13-bit Voltage DACs ■ Two 7-bit Current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin CapSense® Capacitive Sensing ■ Cypress's fourth-generation CapSense Sigma-Delta (CSD) providing best-in-class signal-to-noise ratio (SNR) and water tolerance ■ Cypress-supplied software component makes capacitive sensing design easy ■ Automatic hardware tuning (SmartSense™) Segment LCD Drive ■ LCD drive supported on all pins (common or segment) ■ Operates in Deep-Sleep mode with four bits per pin memory Programmable Digital Peripherals ■ Three independent serial communication blocks (SCBs) that are run-time configurable as I2C, SPI or UART ■ Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks with center-aligned, edge, and pseudo-random modes 32-bit Signal Processing Engine ■ ARM Cortex-M0+ CPU up to 48 MHz ■ Up to 32 KB of flash with read accelerator ■ Up to 4 KB of SRAM ■ Eight-channel descriptor-based DMA controller Low-Power Operation ■ 1.
71-V to 5.
5-V operation ■ Deep-Sleep mode with ...


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