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894D115I-04

Renesas

Clock/Data Recovery

OC-12/STM-4 AND OC-3/STM-1 Clock/Data Recovery Device 894D115I-04 Data Sheet General Description The 894D115I-04 is a ...


894D115I-04

Renesas


Octopart Stock #: O-1417011

Findchips Stock #: 1417011-F

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Description
OC-12/STM-4 AND OC-3/STM-1 Clock/Data Recovery Device 894D115I-04 Data Sheet General Description The 894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals of the device are the recovered clock and retime
More View d data signals. Input and output are differential signals for best signal integrity and to support high clock and data rates. All control inputs and outputs are single-ended signals. An internal PLL is used for clock generation and recovery. An external clock input is provided to establish an initial operating frequency of the clock recovery PLL and to provide a clock reference in the absence of serial input data. The device supports a signal detect input and a lock detect output. A bypass circuit is provided to facilitate factory tests. Features • Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3) • Input: NRZ data (622.08 or 155.52 Mbit/s) • Output: clock signal (622.08MHz or 155.52MHz) and retimed data signal at 622.08 or 155.52 Mbit/s • Internal PLL for clock generation and clock recovery • Differential inputs can accept LVPECL levels • Differential LVDS data and clock outputs • Lock reference input and PLL lock output • 19.44MHz reference clock input • Full 3.3V supply mode • -40°C to 85°C operating temperature • Available in lead-free (RoHS 6) package • See 894D115I for a clock/data recovery circuit with a TSSOP EPAD package and LVPECL outputs • See 894D115I-01 for a clock/data recovery circuit with LVPECL outputs Block Diagram CAP nCAP DATA_IN Pulldown nDATA_IN Pullup/Pulldown REF_CLK Pulldown STS12 Pulldown SD Pulldown LOCK_REFN Pullup BYPASS Pulldown PLL 0 1 DATA_OUT nDATA_OUT CLK_OUT nCLK_OUT LOCK_DET Pin Assignment VDDA DATA_IN nDATA_IN GND_PLL LOCK_DET STS12 REF_CLK LOCK_REFN GND VDD 1 2 3 4 5 6 7 8 9 10 20 VDDA 19 GND_PLL 18 CAP 17 nCAP 16 BYPASS 15 SD 14 DATA_OUT 13 nDATA_OUT 12 CLK_OUT 11 nCLK_OUT 894D115I-04 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ©2016 Integrated Device Technology, Inc 1 Revision C January 27, 2016 894D115I-04 Data Sheet Functional Description The 894D115I-04 is designed to extract the clock from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signals. The output signals are the recovered clock and retimed data signals. The device contains an integrated PLL for clock generation and to lock the output clock to the input data stream. The PLL attempts to lock to the reference clock input (REF_CLK) in absence of the serial data stream or if it is forced to by the control inputs LOCK_REFN or SD. The output clock frequency is controlled by the STS12 input. The output frequency is 622.08MHz in STM-4/OC-12/STS-12 mode and 155.52MHz in STM-1/OC-3/STS-3 mode.






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