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SN74LS192

ON Semiconductor
Part Number SN74LS192
Manufacturer ON Semiconductor
Description UP/DOWN COUNTER
Published Mar 25, 2020
Detailed Description SN74LS192 PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER http://onsemi.com The SN54/...
Datasheet PDF File SN74LS192 PDF File

SN74LS192
SN74LS192

Overview
SN74LS192 PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER http://onsemi.
com The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter.
Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously.
The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs.
Individual preset inputs allow the circuits to be used as programmable counters.
Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.
• Low Power .
.
.
95 mW Typical Dissipation • High Speed .
.
.
40 MHz Typical Count Frequency • Synchronous Counting • Asynchronous Master Reset and Parallel Load • Individual Preset Inputs • Cascading Circuitry Internally Provided PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER LOW POWER SCHOTTKY 16 1 16 1 J SUFFIX CERAMIC CASE 620-09 N SUFFIX PLASTIC CASE 648-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC P0 MR TCD TCU PL P2 P3 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
1 2 3 4 56 78 P1 Q1 Q0 CPD CPU Q2 Q3 GND PIN NAMES LOADING (Note a) HIGH LOW 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 11 15 1 10 9 CPU CPD MR Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input 0.
5 U.
L.
0.
5 U.
L.
0.
5 U.
L.
0.
25 U.
L.
0.
25 U.
L.
0.
25 U.
L.
PL Asynchronous Parallel Load (Active LOW) Input 0.
5 U.
L.
0.
25 U.
L.
Pn Parallel Data Inputs 0.
5 U.
L.
0.
25 U.
L.
Qn Flip-Flop Outputs (Note b) 10 U.
L.
5 (2.
5) U.
L.
TCD Terminal Count Down (Borrow) Output (Note b) 10 U.
L.
5...


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