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SN74LS109A

ON Semiconductor
Part Number SN74LS109A
Manufacturer ON Semiconductor
Description Dual JK Positive Edge-Triggered Flip-Flop
Published May 20, 2005
Detailed Description SN74LS109A Dual JK Positive Edge−Triggered Flip−Flop The SN74LS109A consists of two high speed completely independent tr...
Datasheet PDF File SN74LS109A PDF File

SN74LS109A
SN74LS109A

Overview
SN74LS109A Dual JK Positive Edge−Triggered Flip−Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops.
The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop by simply connecting the J and K pins together.
MODE SELECT − TRUTH TABLE OPERATING MODE INPUTS SD CD J OUTPUTS K Q Q Set Reset (Clear) *Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) L H X X H L H L X X L H L L X X H H H H h h H L H H l h q q H H h l q q H H l l L H * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input i, h (q) = (or output) one set-up time prior to the LOW to HIGH clock transition.
http://onsemi.
com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage TA Operating Ambient Temperature Range 4.
75 5.
0 5.
25 V 0 25 70 °C IOH Output Current − High IOL Output Current − Low −0.
4 mA 8.
0 mA © Semiconductor Components Industries, LLC, 2006 1 June, 2006 − Rev.
8 16 1 SOEIAJ M SUFFIX CASE 966 ORDERING INFORMATION Device Package Shipping SN74LS109AN 16 Pin DIP 2000 Units/Box SN74LS109AD SOIC−16 38 Units/Rail SN74LS109ADR2 SOIC−16 2500/Tape & Reel SN74LS109AM SOEIAJ−16 See Note 1 SN74LS109AMEL SOEIAJ−16 See Note 1 1.
For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative.
Publication Order Number: SN74LS109A/D SET (SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12) J 2(14) K 3(13) SN74LS109A LOGIC DIAGRAM Q 6(10) Q 7(9) LOGIC SYMBOL 5 11 2 J SD Q 6 14 J SD Q 10 4 CP 12 CP 3 K CD Q 7 13 K C...


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