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DS90C387R

Texas Instruments
Part Number DS90C387R
Manufacturer Texas Instruments
Description 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter
Published Mar 26, 2020
Detailed Description DS90C387R www.ti.com SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014 DS90C387R 85MHz Dual 12-Bit Double Pumped Input ...
Datasheet PDF File DS90C387R PDF File

DS90C387R
DS90C387R

Overview
DS90C387R www.
ti.
com SNLS062G – NOVEMBER 2000 – REVISED JANUARY 2014 DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA Check for Samples: DS90C387R FEATURES 1 •2 Complies with Open LDI Specification for Digital Display Interfaces • 25 to 85MHz Clock Support • Supports VGA through UXGA Panel Resolution • Up to 4.
76Gbps Bandwidth in Dual 24-bit RGB In-to-Dual Pixel Out Application • Dual 12-bit Double Pumped Input DVO Port • Pre-Emphasis Reduces Cable Loading Effects • Drives Long, Low Cost Cables • DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion • Transmitter Rejects Cycle-to-Cycle Jitter (±2ns of Input Bit Period) • Support both LVTTL and Low Voltage Level Input (Capable of 1.
0 to 1.
8V) • Two-Wire Serial Communication Interface up to 400 KHz • Programmable Input Clock and Control Strobe Select • Backward Compatible Configuration with 112MHz LDI and FPD-Link • Optional Second LVDS Clock for Backward Compatibility with FPD-Link Receivers • Compatible with TIA/EIA-644 DESCRIPTION The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution.
It is designed to be compatible with Graphics Memory Controller Hub (GMCH) by implementing two data per clock and can be controlled by a two-wire serial communication interface.
Two input modes are supported: one port of 12-bit( two data per clock) input for 24-bit RGB, and two ports of 12-bit( two data per clock) input for dual 24-bit RGB( 48-bit total).
In both modes, input data will be clocked on both rising and falling edges in LVTTL level operation, or clocked on the cross over of differential clock signals in the low swing operation.
Each input data width will be 1/2 of clock cycle.
With an input clock at 85MHz and input data at 170Mbps, the maximum transmission rate of each LVDS line is 595Mbps, for a aggregate throughput rate of 2.
38Gbps/4.
76Gbps.
It converts 24/48 bits (Single/Dual Pixel 24-bit col...


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