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ADSP-CM407F

Analog Devices
Part Number ADSP-CM407F
Manufacturer Analog Devices
Description Mixed-Signal Control Processor
Published Apr 9, 2020
Detailed Description Mixed-Signal Control Processor with ARM Cortex-M4 and 16-Bit ADCs ADSP-CM402F/CM403F/CM407F/CM408F/CM409F SYSTEM FEATU...
Datasheet PDF File ADSP-CM407F PDF File

ADSP-CM407F
ADSP-CM407F

Overview
Mixed-Signal Control Processor with ARM Cortex-M4 and 16-Bit ADCs ADSP-CM402F/CM403F/CM407F/CM408F/CM409F SYSTEM FEATURES Up to 240 MHz ARM Cortex-M4 with floating-point unit 24-channel analog front end (AFE) with 16-bit ADCs 128K Byte to 384K Byte zero-wait-state L1 SRAM with 16K Byte L1 cache Up to 2M Byte flash memory Single 3.
3 V power supply Package Options: 176-lead (24 mm × 24 mm) LQFP package 120-lead (14 mm × 14 mm) LQFP package 212-ball (19 mm × 19 mm) BGA package Static memory controller (SMC) with asynchronous memory interface that supports 8-bit and 16-bit memories Enhanced PWM units Four 3rd/4th order SINC filter pairs for glueless connection of sigma-delta modulators Hardware-based harmonic analysis engine 10/100 Ethernet MAC with IEEE 1588v2 support Full Speed USB on-the-go (OTG) Two CAN (controller area network) 2.
0B interfaces Three UART ports Two serial peripheral interface (SPI-compatible) ports Three/four synchronous serial ports Eight 32-bit GP timers, three capture timing units Four encoder interfaces, 2 with frequency division One TWI unit, fully compatible with I2C bus standard Lightweight security ANALOG FRONT END Two 16-bit SAR ADCs with up to 24 multiplexed inputs, supporting dual simultaneous conversion in 380 ns (16-bit, no missing codes) ADC controller (ADCC) and DAC controller (DACC) Two 12-bit DACs Two 2.
5 V precision voltage reference outputs (For details, see ADC/DAC Specifications on Page 68) GPIO (40 OR 91) JTAG, SWD, CoreSight™ TRACE PLL & POWER MANAGEMENT FAULT MANAGEMENT SYSTEM CONTROL BLOCKS EVENT CONTROL SECURITY SYSTEM WATCHDOGS L1 CACHE 16K BYTE L1 INSTRUCTION CACHE Cortex-M4 L1 MEMORY UP TO 384K BYTE PARITY-ENABLED ZERO-WAIT-STATE SRAM L3 MEMORY UP TO 2M BYTE FLASH (EXECUTABLE) SYSTEM FABRIC ANALOG FRONT END ADCC DACC 2× ADC 2× DAC HARMONIC ANALYSIS ENGINE (HAE) SINC FILTERS HARDWARE FUNCTIONS PERIPHERALS 1× TWI / I2C 4× QUADRATURE ENCODER 12× PWM PAIRS 8× TIMER 3× CPTMR 2× CAN 3× UART 2× SPI 2x SPO...


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