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AD8600

Analog Devices
Part Number AD8600
Manufacturer Analog Devices
Description 16-Channel/ 8-Bit Multiplying DAC
Published Mar 23, 2005
Detailed Description a FEATURES 16 Independently Addressable Voltage Outputs Full-Scale Set by External Reference 2 µ s Settling Time Double ...
Datasheet PDF File AD8600 PDF File

AD8600
AD8600

Overview
a FEATURES 16 Independently Addressable Voltage Outputs Full-Scale Set by External Reference 2 µ s Settling Time Double Buffered 8-Bit Parallel Input High Speed Data Load Rate Data Readback Operates from Single +5 V Optional ± 6 V Supply Extends Output Range APPLICATIONS Phased Array Ultrasound & Sonar Power Level Setting Receiver Gain Setting Automatic Test Equipment LCD Clock Level Setting R/W CS EN A3 A2 A1 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RS VDD1 CONTROL LOGIC ADDRESS DECODE 16-Channel, 8-Bit Multiplying DAC AD8600* FUNCTIONAL BLOCK DIAGRAM LD VDD2 VREF VCC O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 VEE 16 x 8 DAC REGISTERS 16 8-BIT DAC S 16 x 8 INPUT REGISTERS AD8600 DGND1 DGND2 DACGND GENERAL DESCRIPTION The AD8600 contains 16 independent voltage output digital-toanalog converters that share a common external reference input voltage.
Each DAC has its own DAC register and input register to allow double buffering.
An 8-bit parallel data input, four address pins, a CS select, a LD, EN, R/W, and RS provide the digital interface.
The AD8600 is constructed in a monolithic CBCMOS process which optimizes use of CMOS for logic and bipolar for speed and precision.
The digital-to-analog converter design uses voltage mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to VREF.
The voltage buffers provide an output voltage range that approaches ground and extends to 1.
0 V below VCC.
Changes in reference voltage values and digital inputs will settle within ± 1 LSB in 2 µs.
Data is preloaded into the input registers one at a time after the internal address decoder selects the input register.
In the write mode (R/W low) data is latched into the input register during the positive edge of the EN pulse.
Pulses as short as 40 ns can be used to load the data.
After changes have been submitted to the input registers, the DAC registers are simultaneously updated by a common load EN × LD strobe.
The new analo...


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