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9FGP202A

Part Number	9FGP202A
Manufacturer	Renesas
Description	FREQUENCY TIMING GENERATOR
Published	May 8, 2020
Detailed Description	FREQUENCY TIMING GENERATOR FOR PERIPHERALS DATASHEET 9FGP202A General Description The 9FGP202A is a peripheral clock f...
Datasheet	9FGP202A PDF File

Overview

FREQUENCY TIMING GENERATOR FOR PERIPHERALS DATASHEET 9FGP202A General Description The 9FGP202A is a peripheral clock for Intel Server.
It is driven with a 25MHz crystal and generates CPU outputs up to 400MHz.
An SMBus interface allows full control of the device.
Recommended Application Peripheral Clock for Intel Server Output Features • 1 - 0.
7V current-mode differential CPU pair • 8 - 50MHz output • 1 - DOT 96MHz output • 1 - 33.
33MHz output • 1 - 32.
768KHz output • 2 - 25MHz REF outputs Block Diagram Features/Benefits • Selectable SMBus Address – D0/D1 or C0/C1 • Spread Spectrum capability on CPU and DOT 96MHz clocks • SMBus Control: – M/N and spread programming on CPU and DOT 96MHz clocks via SMBus – Outputs can be disabled via pins or SMBus Key Specifications • Exact synthesis on CPU, RMII and 33.
33MHz clocks • +/- 100ppm frequency accuracy on remaining clocks X1_25 X2_25 XTAL CPU PLL (SPREAD CAPABLE) 25MHz(1:0) CPUCLK VttPwr_GD/PD# OE_CPU OE_96 OE_RMIIA OE_RMIIB SMBADR SMBDAT SMBCLK CONTROL LOGIC DOT PLL (SPREAD CAPABLE) FIXED PLL DIVIDERS 8 DIVIDERS DOT96SS 33.
33MHz RMII(7:0) 32.
768KHz IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS 1 9FGP202A REV D 070511 9FGP202A FREQUENCY TIMING GENERATOR FOR PERIPHERALS Pin Configuration VttPwr_GD/PD# S MBD AT S MBC LK RM II0 RMII 1 GND RMII VDDRMII RMII2 R MII3 OE_ RMIIA 40 39 38 37 36 35 34 33 32 31 GND 1 30 OE_RMIIB VDD96 2 DOT96SST 3 29 RMII4 28 RMII5 DOT96SSC 4 27 GND RMII OE_96 5 OE_CPU 6 9FGP202 26 VDDRMII 25 RMII6 CPUCLKT0 7 24 RMII7 CPUCLKC0 8 23 VDD33 VDDCPU 9 GNDCPU 10 22 33.
33MHZ/**SMBADR 21 GND 33 11 12 13 14 15 16 17 18 19 20 IREF VDD32K 32 .
768K Hz G ND3 2K VDD REF 25MHz_0 25 MHZ_1 GNDREF X 1_2 5 X2 _25 40-MLF * Internal Pull-Up Resistor ** Internal Pull-Down Resistor SMBus Address Selection SM BADR *SMBADR = 0 D0/D1 * Default value SMBADR = 1 C0 /C1 Power Supply Pins Pin Number VD D GND Des cription 9 10 21 CPUCLK output DOT96SS output 26,34 23 27 ,35 21 ...

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