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74FCT38072S

Renesas
Part Number 74FCT38072S
Manufacturer Renesas
Description Low Skew 1 to 2 Clock Buffer
Published May 23, 2020
Detailed Description Low Skew 1 to 2 Clock Buffer 74FCT38072S DATASHEET Description The 74FCT38072S is a low skew, single input to two outp...
Datasheet PDF File 74FCT38072S PDF File

74FCT38072S
74FCT38072S


Overview
Low Skew 1 to 2 Clock Buffer 74FCT38072S DATASHEET Description The 74FCT38072S is a low skew, single input to two output, clock buffer.
The 74FCT38072S has best in class additive phase Jitter of sub 50 fsec.
Renesas makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks.
Contact us for all of your clocking needs.
Features • Low additive phase jitter RMS: 50fs • Extremely low skew outputs (50ps) • Low cost clock buffer • Packaged in 8-pin SOIC and 8-pin DFN, Pb-free • Input/Output clock frequency up to 200 MHz • Low power CMOS technology • Operating voltages of 1.
8V to 3.
3V • Extended temperature range (-40° to +105°C) Block Diagram Q0 ICLK Q1 74FCT38072S FEBRUARY 3, 2023 1 ©2015-2023 Renesas Electronics Corporation 74FCT38072S DATASHEET Pin Assignments VDD 1 VDD 2 ICLK 3 GND 4 8 GND 7 Q1 6 Q0 5 GND 8-pin SOIC VDD 1 VDD 2 ICLK 3 GND 4 8 GND 7 Q1 6 Q0 5 GND 8-pin DFN Pin Descriptions Pin Pin Pin Number1 Name Type Pin Description 1 VDD Power Connect to +1.
8V, +2.
5 V, or +3.
3 V.
2 VDD Power Connect to +1.
8V, +2.
5 V, or +3.
3 V.
3 ICLK Input Clock input.
4 GND Power Connect to ground.
5 GND Power Connect to ground.
6 Q0 Output Clock output 0.
7 Q1 Output Clock output 1.
8 GND Power Connect to ground.
1.
VDD on pin 1 and 2 is the same internal signal and must be connected to the same power rail on the PCB.
External Components A minimum number of external components are required for proper operation.
A decoupling capacitor of 0.
01 µF should be connected between VDD pin and GND pin, as close to the device as possible.
A 33  series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 74FCT38072S is capable of, careful attention must be paid to board layout.
Essentially, both outputs must have identical terminations, identical loads and identical trace geometries.
If they do not, the output skew will be degrad...


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