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S32R372

Part Number	S32R372
Manufacturer	NXP
Description	32-bit CPU
Published	Jul 13, 2020
Detailed Description	NXP Semiconductors Data Sheet: Technical Data S32R372 Data Sheet Features • Dual issue computation cores: Power Architec...
Datasheet	S32R372 PDF File

Overview

NXP Semiconductors Data Sheet: Technical Data S32R372 Data Sheet Features • Dual issue computation cores: Power Architecture® e200z7 32-bit CPU • 1.
3 MB on-chip code flash memory (FMC flash memory) with ECC • 1 MB on-chip SRAM with ECC • RADAR processing – Signal Processing Toolbox (SPT) for RADAR signal processing acceleration – Cross Triggering Engine (CTE) for precise timing generation and triggering – MIPICSI2 interface to connect external RADAR RX ADCs • Memory protection – Each core memory protection unit provides 24 entries – Data and instruction bus system memory protection unit (SMPU) with 16 region descriptors each – Register protection • Clock generation – 40 MHz external crystal (XOSC) – 16 MHz Internal oscillator (IRCOSC) – Dual system PLL with one frequency modulated phase-locked loop (FMPLL) – Low-jitter PLL • Functional safety – Enables ASIL-B applications – Fault Collection and Control Unit (FCCU) for fault collection and fault handling – Memory Error Management Unit (MEMU) for memory error management – Safe eDMA controller – Self-Test Control Unit (STCU2) – Error Injection Module (EIM) – On-chip voltage monitoring – Clock Monitor Unit (CMU) Document Number S32R372 Rev.
4, 08/2018 S32R372 • Security – Cryptographic Security Engine (CSE2) – Supports censorship and life-cycle management • Timers – Two Periodic Interval Timers (PIT) with 32-bit counter resolution – Two System Timer Module (STM) – Two Software Watchdog Timers (SWT) – One eTimer module with 6 channels each – One FlexPWM module for 12 PWM signals • Communication interfaces – Two Serial Peripheral interface (SPI) modules – One LINFlexD module – Two inter-IC communication interface (I2C) modules – Two FlexCAN modules supporting CAN FD with configurable buffers • Debug functionality – 4-pin JTAG interface and Nexus/Aurora interface for serial high-speed tracing – e200z7 core: Nexus development interface (NDI) per IEEE-ISTO 5001-2012 Class 3+ • Two analog-to-digital converters (SAR ADC) – Ea...

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S32R372 32-bit CPU - NXP

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