DatasheetsPDF.com

SM320C6712D-EP

Texas Instruments
Part Number SM320C6712D-EP
Manufacturer Texas Instruments
Description Digital Signal Processor
Published Aug 7, 2020
Detailed Description SM320C6712ĆEP, SM320C6712CĆEP, SM320C6712DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS D Controlled Baseline − One Asse...
Datasheet PDF File SM320C6712D-EP PDF File

SM320C6712D-EP
SM320C6712D-EP

Overview
SM320C6712ĆEP, SM320C6712CĆEP, SM320C6712DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D Low-Price/High-Performance Floating-Point Digital Signal Processors (DSPs): 320C67x (SM320C6712, C6712C, C6712D) − Eight 32-Bit Instructions/Cycle − 100-, 167-MHz Clock Rates − 10-, 6-ns Instruction Cycle Times − 600, 1000 MFLOPS D Advanced Very Long Instruction Word (VLIW) C67x DSP Core − Eight Highly Independent Functional Units: − Four ALUs (Floating- and Fixed-Point) − Two ALUs (Fixed-Point) − Two Multipliers (Floating- and Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Hardware Support for IEEE Single-Precision and Double-Precision Instructions − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D Device Configuration − Boot Mode: 8- and 16-Bit ROM Boot − Endianness: Little Endian (12/12C) Little Endian, Big Endian (12D) SGUS055 − SEPTEMBER 2004 D L1/L2 Memory Architecture − 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) − 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) − 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) D Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) D 16-Bit External Memory Interface (EMIF) − Glueless Interface to Asynchronous Memories: SRAM and EPROM − Glueless Interface to Synchronous Memories: SDRAM and SBSRAM − 256M-Byte Total Addressable External Memory Space D Two Multichannel Buffered Serial Ports (McBSPs) − Direct Interface to T1/E1, MVIP, SCSA Framers − ST-Bus-Switching Compatible − Up to 256 Channels Each − AC97-Compatible − Serial-Peripheral-Interface (SP...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)