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ICS851S201I

Renesas
Part Number ICS851S201I
Manufacturer Renesas
Description Differential-to-HCSL Multiplexer
Published Aug 8, 2020
Detailed Description 2:2 Differential-to-HCSL Multiplexer with Low Input Level Alarm ICS851S201I Datasheet Description The ICS851S201I is a...
Datasheet PDF File ICS851S201I PDF File

ICS851S201I
ICS851S201I

Overview
2:2 Differential-to-HCSL Multiplexer with Low Input Level Alarm ICS851S201I Datasheet Description The ICS851S201I is a high-performance 2-input, 2-output Differential-to-HCSL Multiplexer.
The ICS851S201I operates up to 250MHz and accepts HCSL and other low level differential inputs levels.
Input level detection circuitry is available to flag input levels that drops below a specified value and on the selected input.
This signal is latched until the status is reset via the alarm reset input.
The ICS851S201I is packaged in a small 3mm x 3mm 16 lead VFQFPN package, making it ideal for use on space constrained boards.
Features • Two differential HCSL output pairs • Two selectable differential clock input pairs • CLKx, nCLKx pairs can accept HCSL level inputs • Low level input detection on selected input (latched) • Maximum Input frequency: 250MHz • Output skew: 5ps (typical) • Propagation delay: 1.
4ns (typical) • Additive RMS phase jitter at 133.
33MHz (12kHz - 20MHz): 0.
151ps (typical) • Full 3.
3V operating supply • -40°C to 85°C ambient operating temperature • Lead-free (RoHS 6) packaging Block Diagram CLK0 Pulldown nCLK0 Pullup/Pulldown 0 CLK1 Pulldown nCLK1 Pullup/Pulldown 1 CLK_SEL Pulldown IREF LLAR Pulldown Pin Assignment GND CLK_SEL IREF VDD Q0 nQ0 Q1 nQ1 LLA 16 15 14 13 CLK0 1 12 nQ0 nCLK0 2 11 Q0 CLK1 3 10 nQ1 nCLK1 4 9 Q1 5 6 78 VDD LLAR LLA GND ICS851S201I 16-Lead VFQFPN Top View ICS851S201I FEBRUARY 1, 2018 1 ©2018 Integrated Device Technology, Inc.
ICS851S201I Datasheet 2:2 DIFFERENTIAL-TO-HCSL MULTIPLEXER Pin Descriptions and Characteristics Table 1.
Pin Descriptions Number Name Type 1 CLK0 Input Pulldown 2 nCLK0 Input Pullup/ Pulldown 3 CLK1 Input Pulldown 4 nCLK1 Input Pullup/ Pulldown 5, 13 VDD Power 6 LLAR Input Pulldown 7 8, 16 LLA GND Output Power Description Non-inverting differential HCSL clock input.
Inverting differential HCSL clock input.
VDD/2 default when left floating.
Non-invert...


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