DatasheetsPDF.com

9DBV0431

Part Number	9DBV0431
Manufacturer	Renesas
Description	Zero-delay/Fanout Buffer
Published	Aug 12, 2020
Detailed Description	4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer (ZDB/FOB) 9DBV0431 DATASHEET Description The 9DBV0431 is a member...
Datasheet	9DBV0431 PDF File

Overview

4-output 1.
8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer (ZDB/FOB) 9DBV0431 DATASHEET Description The 9DBV0431 is a member of IDT's SOC-Friendly 1.
8V Very-Low-Power (VLP) PCIe family.
It can also be used for 50M or 125M Ethernet Applications via software frequency selection.
The device has 4 output enables for clock management, and 3 selectable SMBus addresses.
Recommended Application 1.
8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • 4 - 1-200Hz Low-Power (LP) HCSL DIF pairs w/ZO=100ohms Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs rms for 12k-20MHz Block Diagram Features/Benefits • LP-HCSL outputs save 8 resistors; minimal board space and BOM cost • 53mW typical power consumption in PLL mode; minimal power consumption • OE# pins; support DIF power management • HCSL compatible differential input; can be driven by common clock sources • Programmable Slew rate for each output; allows tuning for various line lengths • Programmable output amplitude; allows tuning for various application environments • Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application • Outputs blocked until PLL is locked; clean system start-up • Software selectable 50MHz or 125MHz PLL operation; useful for Ethernet applications • Configuration can be accomplished with strapping pins; SMBus interface not required for device control • 3.
3V tolerant SMBus interface works with legacy controllers • Space saving 32-pin 5x5mm VFQFPN; minimal board space • Selectable SMBus addresses; multiple devices can easily share an SMBus segment vOE(3:0)# 4 CLK_IN CLK_IN# vSADR ^vHIBW_BYPM_LOBW# ^CKPWRGD_PD# SDATA_3.
3 SCLK_3.
3 SSCompatible PLL CONTROL LOGIC DIF3 DIF2 DIF1 DIF0 9DBV0431 REVISION E 04/28/16 1 ©2016 Integrated Device Technology, Inc.
9DBV0431 DATASHEET Pin Configuration ^SADR_tri ^CKPWRGD_PD# GND vOE3...

Similar Datasheet

9DBV0431 4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer - IDT
9DBV0431 Zero-delay/Fanout Buffer - Renesas
9DBV0441 4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB - IDT
9DBV0441 1.8V PCIe Gen1-4 ZDB/FOB - Renesas

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)