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54F109

Part Number	54F109
Manufacturer	Texas Instruments
Description	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP
Published	Nov 23, 2020
Detailed Description	SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCT...
Datasheet	54F109 PDF File

Overview

SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain two independent J-K positive-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse.
Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle flip-flops by grounding K and trying J high.
They also can perform as...

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