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74LV02APW

nexperia
Part Number 74LV02APW
Manufacturer nexperia
Description Quad 2-input NOR gate
Published Dec 27, 2020
Detailed Description 74LV02A Quad 2-input NOR gate Rev. 1 — 19 December 2018 Product data sheet 1. General description The 74LV02A is a qua...
Datasheet PDF File 74LV02APW PDF File

74LV02APW
74LV02APW

Overview
74LV02A Quad 2-input NOR gate Rev.
1 — 19 December 2018 Product data sheet 1.
General description The 74LV02A is a quad 2-input NOR gate.
Inputs are overvoltage tolerant.
This feature allows the use of these devices as translators in mixed voltage environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF.
The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
2.
Features and benefits • Wide supply voltage range from 2.
0 V to 5.
5 V • Maximum tpd of 10 ns at 5 V • Typical VOL(p) < 0.
8 V at VCC = 3.
3 V, Tamb = 25 °C • Typical VOH(v) > 2.
3 V at VCC = 3.
3 V, Tamb = 25 °C • Supports mixed-mode voltage operation on all ports • IOFF circuitry provides partial Power-down mode operation • Latch-up performance exceeds 250 mA per JESD 78 Class II • ESD protection: • MM: MM JESD22-A115-B exceeds 200 V • HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range 74LV02APW -40 °C to +125 °C Name TSSOP14 Description plastic thin shrink small outline package; 14 leads; body width 4.
4 mm Version SOT402-1 Nexperia 4.
Functional diagram 2 1 1 3 2 1A 3 1B 5 2A 6 2B 8 3A 9 3B 11 4A 12 4B 1Y 1 2Y 4 3Y 10 4Y 13 mna216 Fig.
1.
Logic symbol 5 1 4 6 8 1 10 9 11 1 13 12 mna217 Fig.
2.
IEC logic symbol 5.
Pinning information 74LV02A Quad 2-input NOR gate A Y B mna215 Fig.
3.
Logic diagram (one gate) 5.
1.
Pinning 1Y 1 1A 2 1B 3 2Y 4 2A 5 2B 6 GND 7 Fig.
4.
Pin configuration SOT402-1 (TSSOP14) 74LV02A 14 VCC 13 4Y 12 4B 11 4A 10 3Y 9 3B 8 3A aaa-029452 5.
2.
Pin description Table 2.
Pin description Symbol 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B 1Y, 2Y, 3Y, 4Y GND ...


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